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preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 figure: mechanical dimensions 1 4 gb ddr2 C sdram so - dimm 200 pin so - c dimm se c 0 4g 72c1bc2mt - xx r 4 gb pc2 - 53 00 in fbga techn ology rohs compliant environmental requirements: ? operating temperature (ambient ) standard grade 0c to 70c ? operating humidity 10% to 90% relative humidity, noncondensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c options: ? data rate / latency marking ddr2 667 mt/s cl5 - 30 ddr2 533 mt/s cl4 - 37 ? module density 4096mb with 18 dies and 2 ranks ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c features: ? 200 - pin 72 - bit small outline clocked dual - i n - line double data rate s ynchronous dram module ? module organization: dual rank 512 m x 72 ? v dd = 1.8v 0. 1 v, v ddq 1.8v 0.1 v ? 1.8v i/o ( sstl_18 compatible) ? serial presence detect with eeprom ? phase - lock loop (pll) clock driver to reduce loading ? supports ecc error detection and correction ? gold - contact pad ? this module is fully pin and functional compatible to the jedec pc2 - 64 00 spec. and jedec - standard mo - 224 . (see www.jedec.org ) ? the pcb and all components are manufactured ac cording to the rohs compliance specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr2 - sdram component micron mt47h256m8eb - 25e:c ? 256 mx8 ddr2 sdram in fbga - 60 package ? four bit prefetch architecture ? dll to align dq and dqs transitions with ck ? eight internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency C 1 t ck ? programmable burst length: 4 or 8 ? adjustable data - output drive strength ? on - die term ination (odt) 1 if no tolerances specified 0.15mm
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 this swissbit module is an industry standard 200 - pin 8 - byte ddr2 sdram clocked small outline dual - in - li ne memory module (so - c dimm) which is organized as x64 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr2 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr2 sdram modules oper ate from a differential clock (ck and ck#). read and write accesses to a ddr2 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr2 sdram devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_18 compatible. the ddr2 sdram module uses the optional serial presence detect (spd) function implemente d via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the so - dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing param eters. the second 128 bytes are available to the end user. module configuration organization ddr2 sdrams used row addr. device bank select column addr. refresh module bank select 512 m x 72 bit 18 x 256 m x 8bit ( 2048 m bit) 1 5 ba0, ba1, ba2 10 8k s0#, s1# module dimensions in mm 67.60 (long) x 30(high) x 3.80 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency se c 0 4 g 72c1 b c 2 mt - 37 r 4096 mb 4.2 gb/s 3.5ns/533 mt/s 4 - 4 - 4 sec04g72c1bc2mt - 30r 4096 mb 5.3 gb/s 3.0ns/667mt/s 5 - 5 - 5 pin name a0 C a9 , a11 C a1 4 address inputs a10/ap address input / autoprecharge bit ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C cb7 ecc check bits dm0 C dm8 input data mask dqs0 C dqs 8 data st robe, positive line dqs0# - dqs 8 # data strobe, negative line (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable ck0 C ck1 clock inputs, positive line figure 1: mechanical dimensions
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ck0# - ck1# clock inputs, negative line s0# - s1# chip select v dd supply voltage (1.8v 0.1v) v ref input / output reference v ss ground v ddspd serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0 C odt1 on - die termination nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 v ref 2 v ss 101 a1 102 a0 3 v ss 4 dq4 103 v dd 104 v dd 5 dq0 6 dq5 105 a10/ap 106 ba1 7 dq1 8 v ss 107 ba0 108 ras# 9 v ss 10 dm0 109 we# 110 s0# 11 dqs0# 12 v ss 111 v dd 112 v dd 13 dqs0 14 dq6 113 cas# 114 odt0 15 v ss 16 dq7 115 s1# 116 a13 17 dq2 18 v ss 117 v dd 118 v dd 19 dq3 20 dq12 119 odt1 120 nc (s3) 21 v ss 22 dq13 121 v ss 122 v ss 23 dq8 24 v ss 123 dq32 124 dq36 25 dq9 26 dm1 125 dq33 126 dq37 27 v ss 28 v ss 127 v ss 128 v ss 29 dqs1# 30 ck0 129 dqs4# 130 dm4 31 dqs1 32 ck0# 131 dqs4 132 v ss 33 v ss 34 v ss 133 v ss 134 dq38 35 dq10 36 dq14 135 dq34 136 dq3 9 37 dq11 38 dq15 137 dq35 138 v ss 39 v ss 40 v ss 139 v ss 140 dq44 41 v ss 42 v ss 141 dq40 142 dq45 43 dq16 44 dq20 143 dq41 144 v ss 45 dq17 46 dq21 145 v ss 146 dqs5# 47 v ss 48 v ss 147 dm5 148 dqs5 49 dqs2# 50 nc (event#) 149 v ss 150 v ss 51 dqs2 52 d m2 151 dq42 152 dq46
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 pin # front side pin # back side pin # front side pin # back side 53 v ss 54 v ss 153 dq43 154 dq47 55 dq18 56 dq22 155 v ss 156 v ss 57 dq19 58 dq23 157 dq48 158 dq52 59 v ss 60 v ss 159 dq49 160 dq53 61 dq24 62 dq28 161 v ss 162 v ss 63 dq25 64 dq29 163 nc (test) 164 ck1 65 v ss 66 v ss 165 v ss 166 ck1# 67 dm3 68 dqs3# 167 dqs6# 168 v ss 69 nc (reset#) 70 dqs3 169 dqs6 170 dm6 71 v ss 72 v ss 171 v ss 172 v ss 73 dq26 74 dq30 173 dq50 174 dq54 75 dq27 76 dq31 175 dq51 176 dq55 77 v ss 78 v ss 177 v ss 178 v ss 79 cke0 80 cke1 179 dq56 180 dq60 81 v dd 82 v dd 181 dq57 182 dq61 83 nc (s2#) 84 nc (a15) 183 v ss 184 v ss 85 ba2 86 a14 185 dm7 186 dqs7# 87 v dd 88 v dd 187 v ss 188 dqs7 89 a12 90 a11 189 dq58 190 v ss 91 a9 92 a7 191 dq59 192 d q62 93 a8 94 a6 193 v ss 194 dq63 95 v dd 96 v dd 195 sda 196 v ss 97 a5 98 a4 197 scl 198 sa0 99 a3 100 a2 199 v ddspd 200 sa1 (sig): signal in brackets may be routed to the socket connector, but is not used on the module
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 functional block diagramm 4096 mb ddr2 sdram so - c dimm, 2 ranks and 1 8 components dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 17 v refdq v refca d 0 - d 17 d 0 - d 17 d 0 - d 17 v ss ck 0 , ck 1 notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details . i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 9 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 10 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 11 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 12 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 13 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 14 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 15 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 16 dqs cs s 1 cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 8 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 17 dqs cs ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 17 a 0 - a 14 a 0 - a 14 : sdram d 0 - d 17 ras ras : sdram d 0 - d 17 cas cas : sdram d 0 - d 17 we we : sdram d 0 - d 17 odt 0 odt : sdram d 0 - d 8 cke 1 cke : sdram d 9 - d 17 ck : sdram d 0 - d 17 ck 0 , ck 1 ck : sdram d 0 - d 17 reset reset : sdram d 0 - d 17 cke 0 cke : sdram d 0 - d 8 odt 1 odt : sdram d 9 - d 17 dqs 8 dm 8 dqs 8
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 1.0 2.3 v i/o supply voltage v dd q - 0.5 2.3 v v dd l supply voltage v dd l - 0.5 2.3 v voltage on any p in relative to v ss v in , v out - 0.5 2.3 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 40 40 ck, ck# - 20 20 dm - 5 5 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 16 16 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v dd q 1.7 1.8 1.9 v v dd l supply voltage v dd l 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt v ref C ref v ref + 0.04 v input high (logic 1) v oltage v ih (dc) v ref + 0.125 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.25 - v input low (logic 0) voltage v il (ac) - v ref - 0.25 v capacitance at ddr2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 i dd specifications and conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) parameter & test condition symbol 5300 - 555 4200 - 444 unit operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high betwe en valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 648 624 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 696 656 ma precharge power - down current: all devic e banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref i dd2p 192 192 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high ; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 672 624 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once e very two clock cycles; dq inputs changing once per clock cycle i dd2n 736 672 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast pdn exit m r[12] = 0 i dd3p 256 480 ma slow pdn exit mr[12] = 1 256 160 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 800 720 ma
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 parameter & test condition symbol 5300 - 555 4200 - 444 unit operating read current: all device banks open, continuous burst reads; one mo dule rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1056 936 ma operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between vali d commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 976 896 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 2400 2240 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are float ing at v ref ; dqs are floating at v ref i dd6 192 192 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1536 1376 ma timing values used for i dd measurement symbol 5300 - 5 - 5 - 5 4200 - 4 - 4 - 4 unit cl (i dd ) 5 4 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) 7.5 7.5 ns t ck (i dd ) 3.0 3.75 ns t ras min (i dd ) 45 45 ns t ras max (i dd ) 70000 70000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 195 195 ns
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr2 sdram component electrical characteristics and recommended a c operating conditions (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 5 - 5 - 5 4200 - 4 - 4 - 4 unit parameter symbol min max min max clock cycle time cl = 6 t ck (6) - - - - ns cl = 5 t ck (5) 3.0 8.0 - - ns cl = 4 t ck (4) 3.75 8.0 3 .75 8.0 ns cl = 3 t ck (3) 5.0 8.0 5.0 8.0 ns ck high - level width t ch 0.45 0.55 0.45 0.55 t ck ck low - level width t cl 0.45 0.55 0.45 0.55 t ck half clock period t hp min (t ch, t cl ) - min (t ch, t cl ) - ps access window (output) of dq s from ck/ck# t ac - 0.45 +0.45 - 0.50 +0.50 ns data - out high - impedance window from ck/ck# t hz - +0.45 (= t ac max) - +0.50 (= t ac max) ns data - out low - impedance window from ck/ck# t lz - 0.45 (= t ac min) +0.45 (= t ac max) - 0.50 (= t ac min) +0.50 (= t ac max) ns dq and dm input setup time relative to dqs t ds 0.10 - 0.10 - ns dq and dm input hold time relative to dqs t dh 0.30 - 0.35 - ns dq and dm input pulse width ( for each input ) t dipw 0.35 - 0.35 - t ck data hold skew factor t qhs - 0.34 - 0.4 ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh t hp - t qhs - t hp - t qhs - ns data valid output window t dvw t qh - t dqsq - t qh - t dqsq - ns dqs input high pulse width t dqsh 0.35 - 0.35 - t ck dqs input low pulse width t dqsl 0.35 - 0.35 - t ck dqs falling edge to ck rising - setup time t dss 0.2 - 0.2 - t ck dqs falling edge from ck rising - hold time t dsh 0.2 - 0.2 - t ck dqs C t dqsq - 0.24 - 0.30 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dqs write preamble t wpre 0.35 - 0.25 - t ck dqs write preamble setup time t wpres 0 - 0 - ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck write command to first dqs latching transition wl - t dqss wl+ t dqss wl - t dqss wl+ t dqss t ck address and control input pulse width ( for each input ) t ipw 0.6 - 0.6 - t ck address and control input setup time t isa 0.4 - 0.5 - ns
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr2 sdram component ele ctrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 5 - 5 - 5 4200 - 4 - 4 - 4 unit parameter symbol min max min max address and control input hold time t ih 0.4 - 0.5 - ns cas# to cas# command delay t ccd 2 - 2 - t ck active to active (same bank) command period t rc 60 - 60 - ns active bank a to active bank b command t rrd 7.5 - 7.5 - ns active to read or write delay t rcd 15 - 15 - ns four bank activate period t faw 37.5 - 37.5 - ns active to precharge command t ras 40 70 t rtp 7.5 - 7.5 - ns write recovery time t wr 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp - t wr + t rp - ns internal write to read command delay t wtr 7.5 - 7.5 - ns pre charge command period t rp 15 - 15 - ns precharge all command period t rpa t rp + t ck - t rp + t ck - ns load mode command cycle time t mrd 2 - 2 - t ck cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t ck refresh to active or refresh to refresh command interval t rfc 195 70 (0c<= t case <= 85 c) t refi - 7.8 - 7.8 s (85c<= t case <= 95 c) t refi (it) 3.9 3.9 exit self refresh to non - read command t xsnr t rfc (min ) + 10 - t rfc (min) + 10 - ns exit self refresh to read command t xsrd 200 - 200 - t ck exit self refresh timing reference t isxr t is - t is - ps odt turn - on delay t aond 2 2 2 2 t ck odt turn - on t aon t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1,000 ps od t turn - off delay t aofd 2.5 2.5 2.5 2.5 t ck odt turn - off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn - on (power - down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn - of f (power - down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power - down entry latency t anpd 3 - 3 - t ck
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 ddr2 sdram component electrical characteristics and recommended ac operating con ditions (continued) (0c t case + 85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v) ac characteristics 5300 - 5 - 5 - 5 4200 - 4 - 4 - 4 unit parameter symbol min max min max odt power - down exit latency t axpd 8 - 8 - t ck odt enable from mrs command t mod 12 - 12 - ns exit active powe r - down to read command, mr [bit 12 = 0] t xard 2 - 2 - t ck exit active power - down to read command, mr [bit 12 = 1] t xards 7 C C ck exit precharge power - down to any non - read command t xp 2 - 2 - t ck cke minimum high/low time t cke 3 - 3 - t ck
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 serial presence - detect matrix byte description 5300 - 5 - 5 - 5 4200 - 4 - 4 - 4 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x 08 2 fundamental memory type 0x 08 3 number of row addresses on assembly 0x 0 f 4 number of column address es on assembly 0x 0a 5 dimm hight and module ranks 0x61 6 module data width 0x 4 8 7 module data width (continued) 0x 00 8 module voltage interface levels (v dd q ) 0x 05 9 sdram cycle time, (t ck ) [max cl] cl = 6 (6400), cl = 5 (5300), cl = 4 (4200) 0x 30 0x 3 d 10 sdram access from clock, (t ac ) [max cl] cl = 6 (6400), cl = 5 (5300), cl = 4 (4200) 0x 45 0x 50 11 module configuration type 0x 0 2 12 refresh rate / type 0x 82 13 sdram device width (primary sdram) 0x 08 14 error - checking sdram data width 0x 0 8 15 mi nimum clock delay, back - to - back random column access 0x 00 16 burst lengths supported 0x 0c 17 number of banks on sdram device 0x 08 18 cas latencies supported 0x 38 0x18 19 module thickness 0x 01 20 ddr2 dimm type 0x 0 6 21 sdram module attributes 0x 0 4 22 sdram device attributes: weak driver and 50 ? odt 0x 03 0x01 23 sdram cycle time, (t ck ) [max cl C 1] cl = 5 (6400), cl = 4 (5300), cl = 3 (4200) 0x 3d 0x50 24 sdram access from ck, (t ac ) [max cl C 1] cl = 5 (6400), cl = 4 (5300), cl = 3 (4200) 0x45 0x50 2 5 sdram cycle time, (t ck ) [max cl C 2] cl = 4 (6400), cl = 3 (5300) 0x 50 0x00 26 sdram access from ck, (t ac ) [max cl C 2] cl = 4 (6400), cl = 3 (5300) 0x 45 0x00 27 minimum row precharge time, (t rp ) 0x 3c 28 minimum row active to row active, (t rrd ) 0x 1e 29 minimum ras# to cas# delay, (t rcd ) 0x 3c 30 minimum ras# pulse width, (t ras ) 0x 2d 31 module bank density 0x0 2
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 serial presence - d e tect matrix (continued) byte description 5300 - 5 - 5 - 5 4200 - 4 - 4 - 4 32 address and command setup time, (t isb ) 0x 20 0x 25 33 address and command hold time, (t ihb ) 0x 27 0x 37 34 data / data mask input setup time, (t dsb ) 0x 10 35 data / data mask input hold time, (t dhb ) 0x 17 0x 22 36 write recovery time, (t wr ) 0x 3c 37 write to read command delay, (t wtr ) 0x1e 38 read to precharge command delay, (t rtp ) 0x 1e 39 mem analysis probe 0x 00 40 extension for bytes 41 and 42 0x 06 41 min active auto refresh time, (t rc ) 0x 3 c 42 minimum auto refresh to active / auto refresh command period, (t rfc) 0x 7f 43 sdram device max cycle time, (t ck max ) 0x 80 44 sdram device max dqs - dq skew time, (t dqsq ) 0x 18 0x 1e 45 sdram device max read data hold skew factor, (t qhs ) 0x 22 0x 28 46 pll relock time 0x 0f 47 - 61 optional features, not supported 0x 00 62 spd revision 0x 1 3 63 checksum for bytes 0 - 62 0x 1 9 0x 9b 64 - 66 manufacturer`s jedec id code 0x 7f 67 manufacturer`s jedec id code (continued) 0x da 68 - 71 reserved 0x00 72 manufacturing location 0x01 (switzerland) | 0x02 (germany) | 0x03 (usa) 73 - 90 module part number (ascii) se c 0 4g72c1bc2mt - xx 91 p cb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) x 128 - 255 open for customer use 0xff part number cod e s e c 0 4 g 72 c1 b c 2 mt - 30 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr2 - 667 m t/s sdram d dr 2 200 pin so - cdimm chip vendor ( m icron ) capacity ( 4 gb yte ) 2 module rank width (72bit) chip rev. c pcb - type ( ba2s7rcc 0.10 ) chip organisation x8 * optional / additional information
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 revision history revision changes date 0. 9 preliminary revision 27.08 .2012
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 locations swissbit ag indu striestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 5 4 C 55 _____________________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, sugina mi - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
preliminary data sheet rev.0.9 27.08.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 16 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare und er our sole responsibility that the product product type: 4 gb ddr2 ecc so - cdimm brand name: swissmemory? product series: ddr 2 so - cdimm part number: sec04g72c1bc2mt - xxxr to which this declaration relates is in conformity with the following directives : 2002/96/ec category 3 (weee) following the provisions of directive restriction of the use of certain hazardous substances 2011/65/eu swissbit ag, april 2013 manuela k?gel head of quality management

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